• 启动日期：2018-09-30
• 招聘部门：技术设计
• 汇报对象：无
• 下属人数：无

• 职位描述：

• JOB DESCRIPTION:
  - Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow
  - Do SoC/IP level synthesis / timing analysis / formality check / CDC check
  - Deliver constraints and closely co-work timing closure with P&R
  - Take some block level RTL coding
  QUALIFICATION:
  - MSEE with >3 year+ experience of digital design experience;
  - Relevant experience in complex timing closure;
  - Be familiar with DC/PT/formality check tools
  - Be familiar with Tcl/Perl/…. Scripts language
  - RTL coding experience is a plus

• 年龄要求：25-40岁

  工作年限：3年以上

• 学历要求：本科及以上

  专业要求：不限

• 是否统招：统招

  语言要求：无

专注于云计算市场