• 启动日期：2018-10-25
• 招聘部门：技术设计
• 汇报对象：无
• 下属人数：无

• 职位描述：

• JOB DESCRIPTION:
  
  - Generate sub-module design specification from prototype architecture;
  
  - High-speed circuit design, including RTL coding, IP using, simulation, timing closure and bit file generation;
  
  - Porting ASIC to FPGA, generate/run/debug test cases on FPGA;
  
  - Design report generation
  
  - Build up and maintain FPGA test platforms, including PCB schematic design and layout support;
  
  QUALIFICATION:
  
  - BSEE, more than 2 years circuit design experience with FPGA;
  
  - More experience in IP using/debug, such as PLL, MCU, PCIe, DDR4 interface etc;
  
  - Knowledge of DDR4 memory system and Intel server platform
  
  - Familiar with lab equipments, such as oscilloscope, logic analyzer, etc;
  
  - Familiar with PLD/FPGA design flow using Verilog and EDA tools such as Xilinx ISE, Altera Quartus;
  
  - Know the TPM, encryption IP etc is plus.

• 年龄要求：25-35岁

  工作年限：2年以上

• 学历要求：本科及以上

  专业要求：不限

• 是否统招：统招

  语言要求：无

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